1. Field of the Invention
The invention relates generally to an address transition detecting circuit. More particularly, the invention is concerned with an address transition detecting circuit capable of preventing generation of unnecessary address transition detection signal pulses when glitch is generated and thus stably driving semiconductor chips even at a high power supply voltage, by including a control means for controlling charge/discharge of a given portion of the address transition detecting circuit and a noise removing circuit for removing the address transition detection signal included in the noise at an output terminal of the address transition detecting circuit, in order to remove noises of the address transition detection signal generated by a glitch signal included in a given signal applied to an input terminal of the address transition detecting circuit.
2. Description of the Prior Art
The intensity of semiconductor memory devices becomes higher and its access speed to data becomes also higher. This results from that the processing speed of a microprocessor is further higher. The semiconductor memory devices adopt various technologies for higher operation. One of them is an address transition detecting circuit (hereinafter called xe2x80x9cATDxe2x80x9d).
An operation principle of the ATD will be shortly described as follows.
The ATD detects an address transition inputted outside the chip to internally generate a pulse and internal circuits are synchronized to this pulse to allow a higher operation of the chip.
Referring now to FIG. 1, there is shown a detailed circuit diagram of a conventional ATD.
The ATD includes an address pad 100 for receiving a drain signal ADD as an input to output an address pad signal APAD, an address buffer 101 for internally buffering the address pad signal APAD through the address pad 100, a first pulse detecting unit 102 for detecting a first transition of an output signal AF of the address buffer 101, a second pulse detecting unit 103 for detecting a second transition of an output signal AF of the address buffer 101, a voltage fall unit 105 for falling the power supply voltage applied to the first pulse detecting unit 102 and the second pulse detecting unit 103 to a given voltage, and an output unit 104 for inverting the output signals of the first pulse detecting unit 102 and the second pulse detecting unit 103.
The first pulse detecting unit 102 includes a third inverting means 1 connected to an output terminal of the first inverting means I1 for inverting the address buffer signal AF, for inverting an output signal of the first inverting means I1; a first buffering means 3 connected to an output terminal of the third inverting means 1, for stabilizing an output signal of the third inverting means 1 to a given potential; a first delay means 5 connected between a first node Q1 connected to an output terminal of the third inverting means 1 and a ground terminal Vss; and a fifth inverting means 7 connected between the power supply terminal Vcc and the ground terminal Vss, for inverting the potential of the first node Q1.
Also, the second pulse detecting unit 103 includes a second inverting means I2 for inverting an output signal of the first inverting means I1; a fourth inverting means 2 for inverting an output signal of the second inverting means 12; a second buffering means 4 for stabilizing an output signal of the fourth inverting means 2 to a given potential; a second delay means 6 connected between the second node Q2 connected to an output terminal of the fourth inverting means 2 and the ground terminal Vss; and a sixth inverting means 8 connected between the power supply terminal Vcc and the ground terminal Vss, for inverting the potential of the second node Q2.
The output unit 104 includes a seventh inverting means I3 for inverting one of the output signals from the output terminal of the first pulse detecting unit 102 or the second pulse detecting unit 103 to output an address transition detection signal ATDout.
The voltage fall unit 105 includes a first PMOS transistor P1 and a first resistor R1, which are in parallel connected between the power supply terminal Vcc and the second resistor R2. The first PMOS transistor P1 is driven by the first signal DPD that is generated in an external signal generating circuit.
The third inverting means 1 includes the second PMOS transistor P2 and the first NMOS transistor N1, which are serially connected between the second resistor R2 and the ground terminal Vss. The fourth inverting means 2 includes the third PMOS transistor P3 and the second NMOS transistor N2, which are serially connected between the second resistor R2 and the ground terminal Vss.
The first buffering means 3 includes a first capacitor C1 connected between the power supply terminal Vcc and the first node Q1, and a second capacitor C2 connected between the ground terminal Vss and the first node Q1. The second buffering means 4 includes a third capacitor C3 connected between the power supply terminal Vcc and the second node Q2, and a fourth capacitor C4 connected between the ground terminal Vss and the second node Q3.
The first delay means 5 includes the fourth PMOS transistor P4 and the fifth capacitor C5, which are connected between the first node Q1 and the ground terminal Vss. The second delay means 6 includes the fifth PMOS transistor P5 and the sixth capacitor C6, which are connected between the second node Q2 and the ground terminal Vss. The fourth PMOS transistor P4 and the fifth PMOS transistor P5 are driven by a second signal OPC generated in an external signal generating circuit.
The fifth inverting means 7 includes a sixth PMOS transistor P6 connected between the power supply terminal Vcc and the ground terminal Vss and driven depending on an output signal of the first inverting means I1; a seventh PMOS transistor P7 driven by the potential of the first node Q1, for inverting the potential of the first node Q1; and a fourth NMOS transistor N4 driven depending on the output signals of the third NMOS transistor N3 and the second inverting means I2.
The sixth inverting means 8 includes an eighth PMOS transistor P8 connected between the power supply terminal Vcc and the ground terminal Vss and driven depending on an output signal of the second inverting means 12; a ninth PMOS transistor P9 and a fifth NMOS transistor N5 driven by the potential of the second node Q2, for inverting the potential of the second node Q2; and a sixth NMOS transistor N6 driven by an output signal of the first inverting means I1.
The ATD circuit constructed as mentioned above detects that the first pulse detecting unit 102 transits the output signal AF of the address buffer 101 from LOW to HIGH, and the second pulse detecting unit 103 transits the output signal AF of the address buffer 101 from HIGH to LOW.
It will be explained in conjunction with the operational timing in FIG. 4. The address signal ADD inputted to the address pad 100 pass through the address buffer 101 and then outputs the address buffer signal AF having the same phase to the address signal ADD inputted to the address pad 100 to apply it to the first pulse detecting unit 102 and the second pulse detecting unit 103.
For example, if the address signal ADD inputted to the address pad 100 is transited from a HIGH state to a LOW state during the period from xe2x80x9cT1xe2x80x9d time to xe2x80x9cT2xe2x80x9d time, the address transition detection signal ATDout the initial state of which is HIGH is transited to a LOW state and is then transited to a HIGH state during the period from xe2x80x9cT2xe2x80x9d time to xe2x80x9cT3xe2x80x9d time when the potential on the second node Q2 is transited from a LOW state to a HIGH state.
In more detail, the address buffer 101 outputs the address buffer signal AF having the same phase to the address pad signal APAD during the period from xe2x80x9cT1xe2x80x9d time to xe2x80x9cT2xe2x80x9d time. The address buffer signal AF is inverted by the first inverting means I1 and is then simultaneously inputted to the first pulse detecting unit 102 and the second pulse detecting unit 103 with a HIGH state.
The address buffer signal AF inverted to be a HIGH state is applied to the third inverting means 1 of the first pulse detecting unit 102 to turn on the first NMOS transistor N1 of the third inverting means 1 and at the time to turn off the second PMOS transistor P2. Therefore, an output signal of the third inverting means 1 is outputted with a LOW state since the potential on the first node Q1 is outputted to the ground terminal Vss via the first NMOS transistor N1.
A LOW state signal outputted on the first node Q1 is stabilized by the first buffering means 3 consisting of the first and second capacitors C1 and C2.
Meanwhile, the sixth PMOS transistor P6 of the fifth inverting means 7 using the output signal of the first inverting means I1 as an input is turned off while the sixth NMOS transistor N6 of the sixth inverting means 8 is turned on. Thereafter, the seventh PMOS transistor P7 using the output signal of the third inverting means 1 as an input is turned on while the third NMOS transistor N3 is turned off.
Also, the output signal of the second inverting means I2 using the output signal of the first inverting means I1 as an input is transited to a LOW state. The third PMOS transistor P3 of the fourth inverting means 2 using the output signal of the second inverting means I2 as an input is turned on while the second NMOS transistor N2 is turned off.
Therefore, the power supply voltage of a HIGH state applied via the voltage fall unit 105 and the second resistor R2 from the power supply terminal Vcc is supplied to the second node Q2 via the third PMOS transistor P3. The potential of a HIGH state supplied to the second node Q2 is stabilized by the second buffering means 4 and is then applied to the ninth PMOS transistor P9 and the fifth NMOS transistor N5 of the sixth inverting means 8. The fifth NMOS transistor N5 is turned on by the potential of a HIGH state while the ninth PMOS transistor P9 is turned off.
Meanwhile, the fourth NMOS transistor N4 of the second inverting means I2 using the output signal of the fifth inverting means 7 as an input is turned off while the eighth PMOS transistor P8 of the sixth inverting means 8 is turned on.
At this time, the potential on the second node Q2 starts to transit to a HIGH state from xe2x80x9ct1xe2x80x9d time when the potential on the first node Q1 is completely transited to a LOW state by the second inverting means I2. That is, at the moment when the potential on the second node Q2 is completely transited to a LOW state and is then applied to the seventh PMOS transistor P7 and the third NMOS transistor N3 of the fifth inverting means 7, the potential on the second node Q2 is maintained to be a LOW state and is then applied to the ninth PMOS transistor P9 and the fifth NMOS transistor N5 of the sixth inverting means 8.
At this time, the sixth PMOS transistor P6 of the fifth inverting means 7 is supplied with a HIGH state signal and is thus turned on, while the fourth NMOS transistor N4 is supplied with a LOW state signal and is thus turned of. Also, the eighth PMOS transistor P8 of the sixth inverting means 8 is supplied with a LOW state signal and is thus turned on, while the sixth NMOS transistor N6 is supplied with a High state signal and is thus turned off.
Due to this the fifth inverting means 7 is maintained to be floated during the period from xe2x80x9cT2xe2x80x9d time to xe2x80x9ct1xe2x80x9d time while the sixth inverting means 8 outputs an output signal of a HIGH state to the seventh inverting means I3 of the output unit 104. The seventh inverting means I3 of the output unit 104 inverts the output signal of a HIGH state to output the address transition detection signal ATDout of a LOW state.
Then, if the potential on the second node Q2 is raised during the period from xe2x80x9ct1xe2x80x9d time to xe2x80x9cT3xe2x80x9d time and is thus transited to a HIGH state, during this time, the ninth PMOS transistor P9 of the sixth inverting means 8 is turned off while the fifth NMOS transistor N5 is turned on. Therefore, the output signals of the ninth PMOS transistor P9 and the fifth NMOS transistor N5 are transited to a LOW state. The output unit 104 inverts the potential of a LOW state again to output the address transition detection signal ATDout of a HIGH state.
However, though the conventional ATD circuit as mentioned above must be driven only when an address is transited, the ATD circuit is driven at the value in which an unwanted noise or glitch such as xe2x80x9cAxe2x80x9d shown in FIG. 4 is included, that is, even at a HIGH state or a LOW state. Therefore, there is a problem that abnormal address transition detection signal ATDout is generated.
It is therefore an object of the present invention to provide an address transition detecting circuit capable of preventing generation of unnecessary address transition detection signal by means of a glitch of an address signal.
In order to accomplish the above object, an address transition detecting circuit according to the present invention is characterized in that it comprises a first detecting means for detecting a first transition of an address buffer signal, by which an external address signal is buffered/outputted; a first control means for controlling the flow of current of the first detecting means so that the output of the first detecting means has a different phase from and the same pulse width to the address buffer signal; a second detecting means for detecting a second transition of the address buffer signal; a second control means for controlling the flow of current of the second detecting means so that the output of the second detecting means has a different phase from and the same pulse width to the address buffer signal; and an output means for inverting the output of the first detecting means or the output of the second detecting means to output an address transition detecting signal.
Also, an address transition detecting circuit according to the present invention is characterized in that it comprises a first detecting means for detecting a first transition of an address buffer signal, by which an external address signal is buffered/outputted; a first control means for controlling the flow of current of the first detecting means so that the output of the first detecting means has a different phase from and the same pulse width to the address buffer signal; a second detecting means for detecting a second transition of the address buffer signal; a second control means for controlling the flow of current of the second detecting means so that the output of the second detecting means has a different phase from and the same pulse width to the address buffer signal; a first output means for inverting the output of the first detecting means or the output of the second detecting means to output a first address transition detecting signal; a noise removing means for removing a noise included in the first address transition detecting signal; and a second output means for inverting the output of the noise removing means to output a second address transition detecting signal.